1. Technical Field
This application relates generally to data processing systems. In particular, this application relates to an interface that enables a processor designed to support NOR flash and static random access memory SRAM devices to use NAND flash and synchronous dynamic random access memory SDRAM components.
2. Description of Related Art
Handheld data processing devices, sometimes known as “personal digital assistants”, are becoming very popular tools for information storage and retrieval, messaging and other functions. Such devices have the ability to store a significant amount of data, including calendar, address book, tasks and numerous other types of data for business and personal use. Most handheld data processing devices have the ability to connect to a personal computer for data exchange, and many are equipped for wireless communications using, for example, conventional email messaging systems.
Cost and space are two significant limiting parameters in handheld data processing devices. As a general rule, reducing the number of chips required by the device also reduces the cost and size of the device, and in some cases energy consumption.
A typical handheld data processing device has a processor for processing the data, which accesses data from a NOR flash chip, which is a non-volatile memory storage device that retains data even when no power is being supplied to the chip. Typically the processor caches data read from NOR flash in SRAM, which is a volatile storage device that retains data only when power is being supplied to the chip (i.e. when the handheld data processing device is on). Accordingly, the processor in conventional handheld data processing devices is designed and programmed to read data from NOR flash and write the data to SRAM for use or modification; and to read data from SRAM and write modified data to NOR flash for long term storage.
Another type of non-volatile memory, known as NAND flash, contains more memory density than a comparable NOR flash chip. NAND flash memory is less expensive than NOR flash; however, whereas data is read out of and written to NOR flash memory one byte at a time, data must be read out of and written to NAND flash memory in blocks or “sectors” of data. For example, reading a 16-bit data value stored in NOR flash requires one read access to the flash device, whereas to read the same 16-bit value from NAND flash requires reading out an entire 512 byte sector. Also, their interfaces are different. The two major differences between SRAM and SDRAM is that SDRAM consumes more energy due to the need for constant refresh operations, and their interfaces are also different.
It is therefore not possible for an existing processor in a handheld data processing device, which is designed to write and read individual bytes, to utilize a NAND flash memory. Even if the processor had NAND flash and SDRAM interfaces, the software architecture would need to be completely redesigned to handle the sector based NAND memory architecture. With its existing software architecture the processor will be unable to process data from NAND flash during normal operation of the device, and would not even be able to boot up because it would not be able to process the boot-up routine. To reconfigure the processor so that it could boot and run using a NAND flash chip, the architecture of the processor would need to be drastically changed, which is an extremely expensive and time consuming process.
Further, in some cases processing speed is also an important feature of a handheld data processing device. Because in a conventional handheld data processing device data is read by the processor from NOR flash and written by the processor to SRAM, and vice versa, the processing speed is reduced by these read and write operations. Further, in a conventional handheld data processing device the LCD display is connected directly to the main processor bus, which also reduces processing speed because of the increased capacitance experienced by the processor on the main bus.
It would accordingly be advantageous to provide an interface which allows an existing NOR flash SRAM-based processor in a handheld data processing device to operate using NAND flash/SDRAM memory components. It would further be advantageous to provide an interface which handles memory control to avoid reductions in the processor's speed caused by read and write operations. It would further be advantageous to provide an interface which handles auxiliary devices, such as the display, to avoid reductions in the processor's speed caused by including a large capacitive interface on the main processor bus.